The present invention relates to a semiconductor memory device and, more specifically, to an EEPROM and EPROM having a floating gate in which the data writing and erasing operations can be performed at a lower voltage than conventional ones.
In most basic floating-gate-type EEPROMs, electrons are controlled to move between the floating gate and the diffusion region on the data line side through the tunnel window provided therebetween. Usually, a tunnel oxide film of the tunnel window is formed with a uniform thickness, and so electrons flow uniformly in the tunnel window plane.
In order to improve the efficiency of injecting electrons into and removing those from the floating gate, there have been proposed some techniques which utilize a poly-silicon surface that is formed into an asperity to enhance an electric field acting on electrons. More specifically, in such techniques, an asperity is provided on the floating gate surface and a charge is taken out to flow into a separate poly-silicon lead, or an injection lead having an asperity is formed under the floating gate and electrons are injected through the injection lead.
In practice, however, the above techniques are associated with the following problems. To inject electrons into the floating gate in the most basic device described above, it is usually required that a high voltage of more than 20 V be applied to the control gate, which necessitates a complex device structure and a large device area. Further, the devices utilizing the poly-silicon asperity still have various problems, for instance, increased wiring which results in complex circuitry and an increased device area.